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BACKGROUND
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SIGNAL SOURCE
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SIGNAL DESTINATION
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LIMITS AND FAULTS
BACKGROUND
Seven Transmitter triggers are monitored for excessive PRF.
Four of the Triggers: POST CHARGE REG, MID PRT, RF GATE, and RF DRIVE (see
figure 11-7 sheet 14) use similar monitoring circuitry. Negative
going triggers at the output of the line receivers encounter a 60us
timer that produces a 60us logic high pulse. The falling edge of
the 60us timer output starts the 600us timer which produces a 600us logic
low pulse. This 600us window, which begins 60us after the leading
edge of the negative going trigger allows any low going trigger that occurs
during the window to reach the fault latch input through the OR gate.
Triggers that occur during the 600us window indicate an excessive PRF.
A second type of excessive PRF monitor circuit monitor the other
three triggers: TRIGCHRG, MODCHRG, and MODDISCHG (see figure 11-7 sheet
13). The operation of the excessive PRF fault detection circuitry
for these three triggers is similar to the circuits on figure 11-7 sheet
14 except that the length of the fault window depends on which transmitter
pulse width is in use. Each negative going trigger exiting a line
receiver encounters a 60us timer that produces a 60us positive pulse.
The falling edge of the 60us timer output starts either the 1.8ms timer
or the 600us timer depending on which PRF mode is active (signals PFNWIDE
and PFNNAR). In short mode 600us logic low pulse is produced from
the 600us timer and in long mode a 1.8ms logic low pulse is produced from
the 1.8ms timer. The output of the timer that is not selected is
held high by a logic low clear input. The output of the selected
timer allows any low going trigger that occurs during the fault latch window
to reach the latch through the AND gate. Separate timers provide
increased protection against excessive PRF for these triggers by optimizing
the fault window width for the selected PRF mode.
SIGNAL SOURCE
The PRF Fault signal is a result of the output of seven input NAND
gate. Each input to the NAND gate is the result of the out put of
the monitoring circuits found on figures 11-7 sheets 13 and 14. If there
are any excessive triggers detected on the Transmitter Control Adapter
(A4) board, one or more of the LEDs (DS1 through
DS7) will be lit. This will cause logic low (see figure 11-7
sheet 12) signals GATEPRF at bubble 1409, DRIVEPRF at bubble 1410, MDPRTPRF
at bubble 1408, MTAAPRF at bubble 1301, MODPRF at bubble 1302, DISCHPRF
at bubble 1303, and PCRPRF at bubble 1407 input to the NAND gate to output
a logic high for a fault.
SIGNAL DESTINATION
A PRF Fault is sent to an OR gate along with PFN switch enable (PFNSWEN-)
to produces a high at the output of the OR gate (signal LNDRVIN).
By enabling the output drivers signal LNDRVIN, allows all seven triggers
to pass through the control adapter board to reach other transmitter functions
when no PRF faults exist and switch settling time is over. PRF FAULT
is combined with FAULT SUM IN ( all other transmitter faults) and PFNSWFLT
to produce the signal FLTSUM at bubble 1203-7. FLTSUM is one
of six signals needed for Transmitter Available (TXAVAIL). At bubble
1202-10 PRF FAULT is routed to the transmitter RMS interface (A3) at bubble
1203 as PRFLIMIT (see figure 11-7 sheet 10). There it is placed on
the
Fault Bus as Transmitter Data (TDATA) at Port04EN-, and also leaves at
bubble 1003-11 to become one of the any faults for FLTSUM. PRFLIMT
also leaves at bubble 1022-1 as PRFFLT-, for the Fault Display Panel where
it will light the lamp for PRF LIMIT.
LIMIT AND FAULTS
PRF LIMIT will light when ever there are two of more the same trigger
per PRT.