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BACKGROUND
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SIGNAL SOURCE
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SIGNAL DESTINATION
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LIMITS AND FAULTS
BACKGROUND
The Arc Detector A6 protects the klystron
tube by optically monitoring the waveguide near the klystron output flange
for the presence of arcs, and by monitoring a sample of the reflected RF
power (derived from UD1DC1J2 via AT10, and
UD3DC1J1
via AT 11) that would indicate a high VSWR (Voltage Standing Wave Ratio).
The arc/vswr protection circuit generates a transmitter fault when either
an arc or high reflected power is detected.
SIGNAL SOURCE
Arc Detector A6 (see figure 11-3 sheet 7) monitors the Klystron
waveguide window with photo diode D3 for presence of visible arcs.
The response of photo diode D3 in the presence of an arc causes the preamplifier
to produce a negative going pulse that momentarily falls below the ARCREF
value. The signal ARC is normally about a tenth of a volt higher
than the comparator reference signal ARCREF. The output of the arc
comparator is a positive going signal named ARCDET that passes through
an OR gate which puts out a signal called FAULT, and is latched as signal
QFAULT (negative going) at the output of the fault latch. The arc
detector also accepts a sample of the transmitter reflected power
from UD1DC1J2 and UD3DC1J1 at A6J2 signal
VSWR. The vswr comparator produces the positive going signal VSWRDET
when the VSWR signal exceeds the vswr comparator reference signal VSWRREF.
A positive voltage bias on the positive input
of the vswr comparator will
produce fault signal VSWRDET if the reflected
power cable is disconnected.
The fault signal FAULT results when either
the ARCDET signal or the VSWRDET signal is produced. The fault latch
holds the FAULT signal at the base for the transistor Q12 with signal QFAULT.
Transistor Q12 sinks current through R28 and provides the active low fault
signal ARCVSWR.
The TRIG IN signal from A1S4 Fault Insert push
button provides a means to insert simulated transmitter arc faults by lighting
LED D2. The test timer accepts signal TRIG IN and produces signal
TEST PULSE that drives the test switch. The test switch turns on
LED D2 to provide a simulated arc.
SIGNAL DESTINATION
ARCVSWR leaves the Arc detector via J1-D for Control and Monitoring
RMS Interface card A3A3 (see figure 11-7 sheet 9) via J34-15. There
it is place on the Fault Bus during Port02EN- as Transmitter Data (TDATA),
it also exit bubble 905-11 to remove Transmitter Available at 905 (see
figure 11-7 sheet 11). Signal WGARCVSWR- is also sent to the Fault
Display Panel A1A1 at bubble 916-1. At bubble 916 (see figure 11-7
sheet 1) WGARCVSWR- goes out to light the lamp for Waveguide Arc.
LIMITS AND FAULTS
Arc Detector monitors the Klystron waveguide window with photo
diode D3 for presence of visible arcs which will cause an ARC FAULT. AT10
is sat to send an VSWR to the Arc Detector when vswr = 3:1 or a 6 db change.
AT11 is sat to send an VSWR to the Arc Detector when vswr = 1.5:1 or a
14 db change from system reflection.